Optimization of double-sampled PWM used within power supplies

The emergence of high-frequency high-voltage power semiconductor devices allows the re-design of AC power supplies for operation at higher pulse frequencies with benefits in reduced loss and improved reliability. Conventional PWM algorithms face a hard limit of the minimum pulse width in certain operation points. This paper discusses and proposes a set of new PWM algorithms able to operate the power stage at higher switching frequency without minimum pulse occurrences. These PWM algorithms follow the Staircase PWM algorithm and use optimization at the pulse level. The implementation of such a non-conventional complex PWM structure is possible in modern FPGA System-on-Chip devices.