Optimization of p-emitter/n-buffer using laser annealing technique in IGBT design

P-emitter and n-buffer layers have been optimized for 1700V planar gate DMOS IGBTs by applying laser annealing technique which can overcome the challenge of thin wafer processes to activate dopants implanted from the backside after wafer backside ground. The modules assembled using new chips combining optimized p-emitter/n-buffer design and backside laser annealing process showed attractive on-state voltage drop of 2.05V which is 0.35V lower than the ones without laser annealing process, and 0.65V lower than the conventional NPTs´. Therefore, the conduction loss is significantly reduced. The overshoot voltage between the collector and the emitter electrodes is reduced about 150V during IGBTs turning-off which improves the device ruggedness due to the achieved softer switching and lower di/dt for laser processed IGBTs. In tradeoff, its turn-off loss is about 0.1J/pulse higher than that without laser annealing process.