Co-simulation methodology for improved design and verification of hardware neural networks

This paper presents a methodology for speeding up the design and verification of process of artificial neural networks (ANNs) in system-on-chip (SoC) hardware with the help of co-simulation. Application of advanced design methodologies for complex designs such as ANNs are important in todays fast moving hardware design industry. However, it is difficult to fully verify the functionality of ANNs when designed in hardware. Most forms of ANN require the use of complex training algorithms, which are difficult to implement in a testbench even with the help of modern interfaces such as SystemVerilog´s DPI-C. The neural network topology selected as the case study for this paper are evolvable block-based neural networks (BbNNs). The case studies employed during the verification process are the XOR problem, driver drowsiness classification, and heart arrhythmia classification. The proposed methodology significantly reduces the verification time required for the design of hardware-based neural networks. This allows complex models applicable a variety of applications to be quickly designed, such as industrial motor controllers or fuzzy systems.