Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

This paper presents a new approach of the lockstep technique to protect FPGA designs with soft core processors against Single Event Upsets (SEUs) and Single-Event Transients (SETs). One of the biggest drawbacks when using the lockstep technique is the processor context saving and restoring latency. Our approach minimizes the latency thanks to a specific architecture and a specifically adapted 8-bit soft core processor. The proposed architecture is also hardened by using ECC code in memory elements. In this way, this approach combines the benefits of fast SEUs detection with fast restoration of the device functionality. This is demonstrated by running a serial communication application hardened with the new lockstep approach and comparing the results with a Triple Modular Redundancy (TMR) implementation. The design has been implemented in a Xilinx Virtex-5 FPGA.