• DocumentCode
    666566
  • Title

    Validation of eHS FPGA reconfigurable low-latency electric and power electronic circuit solver

  • Author

    Belanger, Jean ; Yamane, Akinari ; Yen, A. ; Cense, Sebastien ; Robert, Pierre-Yves

  • Author_Institution
    OPAL-RT Technol., Montreal, QC, Canada
  • fYear
    2013
  • fDate
    10-13 Nov. 2013
  • Firstpage
    5418
  • Lastpage
    5423
  • Abstract
    This paper discusses the validation process and example of power electronic circuits simulated with a general purpose solver implemented on FPGA chips. The `Electric Hardware Solver´ or eHS presented in this paper has the goal to facilitate the usage of FPGA for high-fidelity Hardware-In-the-Loop simulation with sub-microsecond time step by avoiding the difficulties associated with the coding of FPGA devices. Several examples, from very simple to more complex using one or several FPGA boards, are presented and results are compared with traditional simulation software such as SimPowerSystems and PLECS. It will be demonstrated that FPGA-based simulation is now accessible to control and simulation system specialists without requiring any FPGA programming skills. In fact, preparation of FPGA simulation requires only the use of PLECS or SimPowerSystems schematic user interface.
  • Keywords
    field programmable gate arrays; power electronics; FPGA chips; FPGA-based simulation; PLECS; SimPowerSystems schematic user interface; eHS FPGA reconfigurable low-latency electric; electric hardware solver; hardware-in-the-loop simulation; power electronic circuit solver; validation process; Field programmable gate arrays; Integrated circuit modeling; Inverters; Load modeling; Matrix converters; Real-time systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industrial Electronics Society, IECON 2013 - 39th Annual Conference of the IEEE
  • Conference_Location
    Vienna
  • ISSN
    1553-572X
  • Type

    conf

  • DOI
    10.1109/IECON.2013.6700017
  • Filename
    6700017