A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate

Author

Hashemi, SayedMasoud ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA

Volume

49

Issue

8

fYear

2014

fDate

Aug. 2014

Firstpage

1739

Lastpage

1750

Abstract

A two-stage pipelined ADC employs a double-sampling residue amplifier, two interleaved precharged DACs, and a new calibration scheme to correct for residue gain error, offset, and nonlinearity. The coarse and fine stages are implemented as flash ADCs incorporating several techniques to reduce their power, complexity, and kickback noise. Realized in 65 nm CMOS technology and sampling at 1 GHz, the prototype achieves an SNDR of 48 dB at the Nyquist rate and exhibits an FOM of 25 fJ/conversion-step while drawing 7.1 mW from a 1 V supply.

Keywords

CMOS integrated circuits; amplifiers; analogue-digital conversion; digital-analogue conversion; CMOS technology; Nyquist rate; SNDR; calibration scheme; double-sampling residue amplifier; flash ADCs; frequency 1 GHz; gain 48 dB; interleaved precharged DACs; kickback noise; power 7.1 mW; residue gain error; size 65 nm; two-stage pipelined ADC; voltage 1 V; Ash; Capacitance; Capacitors; Clocks; Noise; Resistance; Timing; Double-sampling; nonlinearity; offset calibration; pipelined ADCs; precharged DAC;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2311812

Filename

6784024