3D volumetric display design challenges

This paper presents and analyses several challenges of 3D volumetric display design process. Designs with video transfer and processing requires huge amounts of data bandwidth, thus most of the work is done with high-speed programmable logic chips. Introduction to volumetric technology is given and main design blocks and steps are explained. Results show that it is possible to implement all main building blocks within single Virtex-6 FPGA with higher performance and better spatial parameters, in comparison of previous generation volumetric display.