A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter

A novel Time-to-Digital Converter architecture for high resolution and low power is proposed. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the slow delay line can be frozen by the fast delay line, omitting the power-hungry time capture elements like D-registers or arbiters that are usually employed in a Vernier TDC. The two main issues of the design, the charge kickback between the delay lines and the imperfect freezing are solved with extra circuitry. The overall TDC consists of inverters and transmission gates only. A proof-of-concept design has been simulated in 90nm CMOS with a typical resolution of 10.05 ps, a dynamic energy consumption of 0.232 pJ per conversion and an area of 10.503 μm².