Programmable delay controller allowing frequency synthesis and arbitrary binary waveform generation

Design of a programmable delay controller (PDC) within an aerospace-compatible field-programmable gate array (FPGA) fabric is presented. Although PDC is a common digital block nowadays, the possibility to use it for low-jitter arbitrary frequency generation constrained only by minimum edge-to-edge time still seems to be uncovered. The novel idea of the developed PDC is seamless line delay switching at sampling frequencies corresponding to the generated output frequency, unleashing a possibility of arbitrary binary waveform (frequency) generation. The maximum frequency is constrained only by the FPGA fabric performance, and by idle delay of available multiplexers. Glitch-free operation with no unintentional edges is employed for proper PDC control signal switching. The overall output signal jitter is composed solely of the jitter of input signal and propagation jitter of the delay elements (σ_max = 4.1 ps RMS). Measured resolution of the PDC is ±Δτ_max/2 = ±7.5 ps. Measured temperature drift of the PDC is ~ 30 ps K^_1. An ability of PDC to generate fractional frequency from the input has been demonstrated on a simplified, low-resolution variant, delivering 33.3MHz out of 50 MHz input.