• DocumentCode
    667953
  • Title

    Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination

  • Author

    Chew, Jason ; Mahajan, Uday ; Bajaj, Rajeev ; Mirshad, Iad ; Newcomb, Robert

  • Author_Institution
    Appl. Mater., Singapore, Singapore
  • fYear
    2013
  • fDate
    2-4 Oct. 2013
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Through Silicon Vias (TSV) is a key technology for advanced 3DIC packaging, enabling improved device performance, integration of multiple functions in a single package and form factor reduction. TSV reveal CMP is one of the key processes in this integration scheme [1].
  • Keywords
    chemical mechanical polishing; optimisation; three-dimensional integrated circuits; wafer level packaging; TSV CMP reveal process; advanced 3DIC packaging; device performance; form factor reduction; submonolayer surface contamination; through silicon vias; wafer inspection technique; Copper; Inspection; Optimization; Surface contamination; Surface treatment; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    3D Systems Integration Conference (3DIC), 2013 IEEE International
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • DOI
    10.1109/3DIC.2013.6702318
  • Filename
    6702318
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=667953