• DocumentCode
    667960
  • Title

    Silicon Etch with integrated metrology for through silicon via (TSV) reveal

  • Author

    Mauer, Laura B. ; Taddei, John ; Lawrence, E. ; Youssef, Rabaa ; Olson, Stephen P.

  • Author_Institution
    Solid State Equip. LLC, Horsham, PA, USA
  • fYear
    2013
  • fDate
    2-4 Oct. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Wet etch is a cost-effective process option to reveal through-silicon vias (TSVs). This paper addresses the methodology for using integrated wafer thickness measurements to provide complete process control.
  • Keywords
    elemental semiconductors; etching; integrated circuit measurement; process control; silicon; thickness measurement; three-dimensional integrated circuits; TSV; integrated wafer thickness measurements; process control; silicon etch; through silicon via; Etching; Metrology; Process control; Silicon; Thickness measurement; Three-dimensional displays; Through-silicon vias; TSV; TTV; endpoint detection; reveal height; wet etch;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    3D Systems Integration Conference (3DIC), 2013 IEEE International
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • DOI
    10.1109/3DIC.2013.6702325
  • Filename
    6702325
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=667960