Title :
Silicon Etch with integrated metrology for through silicon via (TSV) reveal
Author :
Mauer, Laura B. ; Taddei, John ; Lawrence, E. ; Youssef, Rabaa ; Olson, Stephen P.
Author_Institution :
Solid State Equip. LLC, Horsham, PA, USA
Abstract :
Wet etch is a cost-effective process option to reveal through-silicon vias (TSVs). This paper addresses the methodology for using integrated wafer thickness measurements to provide complete process control.
Keywords :
elemental semiconductors; etching; integrated circuit measurement; process control; silicon; thickness measurement; three-dimensional integrated circuits; TSV; integrated wafer thickness measurements; process control; silicon etch; through silicon via; Etching; Metrology; Process control; Silicon; Thickness measurement; Three-dimensional displays; Through-silicon vias; TSV; TTV; endpoint detection; reveal height; wet etch;
Conference_Titel :
3D Systems Integration Conference (3DIC), 2013 IEEE International
Conference_Location :
San Francisco, CA
DOI :
10.1109/3DIC.2013.6702325
