Si interposer build-up options and impact on 3D system cost

Author

Velenis, Dimitrios ; Detalle, Mikael ; Marinissen, Erik Jan ; Beyne, Eric

Author_Institution

Imec, Leuven, Belgium

fYear

2013

fDate

2-4 Oct. 2013

Firstpage

1

Lastpage

5

Abstract

The requirements for embedded system functionalities promote stacked integration solutions where interposers are used as large carriers to provide dense interconnections among functional dies. Using the cost model developed at imec, the processing cost of different interposer features is analyzed. Build-up options of various interposer configurations are compared and the additional cost of the interposer component is highlighted. In addition the impact of interposer testing on the system cost is investigated for different interposer substrate areas.

Keywords

elemental semiconductors; integrated circuit interconnections; integrated circuit testing; silicon; three-dimensional integrated circuits; 3D die stacking; 3D system cost; Si; TSV; cost model; dense interconnections; embedded system functionalities; interposer component; interposer configurations; interposer substrate areas; interposer testing; stacked integration; through-silicon-via; Metals; Silicon; Stacking; Substrates; Testing; Three-dimensional displays; Through-silicon vias; 3D die stacking; 3D testing; Interposer; TSV; process cost;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2013 IEEE International

Conference_Location

San Francisco, CA

Type

conf

DOI

10.1109/3DIC.2013.6702367

Filename

6702367