DocumentCode :
668020
Title :
Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration
Author :
Joblot, S. ; Farcy, A. ; Hotellier, N. ; Jouve, A. ; de Crecy, F. ; Garnier, A. ; Argoud, Maxime ; Ferrandon, C. ; Colonna, J.P. ; Franiatte, R. ; Laviron, C. ; Cheramy, S.
Author_Institution :
STMicroelectron., Crolles, France
fYear :
2013
fDate :
2-4 Oct. 2013
Firstpage :
1
Lastpage :
7
Abstract :
Wafer level molding is an important process step in the chip on wafer approach and seems currently required in stacking first process flow. Thermo-mechanical properties of molding material has to be controlled to limit stress induce by CTE mismatch with silicon wafer and also to assure planarization and protection functions. 2D and 3D finite element simulations have been performed to evaluate strain and stress impact at wafer level of material properties of silicone based and epoxy based molding compounds. Impacts of Si interposer thickness, design and chips arrangement on wafer warpage are presented and compared with experimental results.
Keywords :
elemental semiconductors; finite element analysis; moulding; silicon; three-dimensional integrated circuits; 2.5D interposer integration; CTE; Si; chip on wafer; epoxy based molding compounds; finite element simulations; molding material; silicon wafer; silicone; thermo-mechanical properties; wafer level encapsulated materials evaluation; wafer level molding; Bonding; Semiconductor device modeling; Silicon; Stacking; Stress; Three-dimensional displays; 3D integration; Si interposer; chip on wafer; thermomechanical simulations; wafer level molding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
3D Systems Integration Conference (3DIC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Type :
conf
DOI :
10.1109/3DIC.2013.6702394
Filename :
6702394
Link To Document :
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