Face-to-face bus design with built-in self-test in 3D ICs

This paper presents a bus structure, synchronization and test scheme for fast data transfer between logic dies in stacked 3D ICs using face-to-face (F2F) micro-bumps. The proposed design permits different designs, such as microprocessor, co-processor and accelerator, to be integrated together vertically with high bandwidth and low power, which is uniquely enabled by the dense F2F micro-bumps. We propose a new teleport-register-file structure and corresponding clock gating and switching techniques to synchronize data across multiple clock domains. Simultaneous bi-directional transfer is supported and 50% reduction of flip-flops compared with conventional synchronizer design. Moreover, a lightweight built-in-self-test (BIST) unit is integrated into the bus. The BIST unit allows for rapid stuck-at and transition fault testing of the 3D bus interconnects and associated logic, without the need for an external tester. BIST allows field testing and test/validation at later stages of 3D integration. The BIST architecture utilizes the architectures and functions inherent to the bus and requires little extra hardware or dedicated interconnects between dies. Functionality and performance demos are verified and simulated under .13 μm technology. The energy cost estimate is 0.22 pJ/bit and maximum bandwidth per area is 1.42 Tb/mm².