• DocumentCode
    668075
  • Title

    HotStream: Efficient Data Streaming of Complex Patterns to Multiple Accelerating Kernels

  • Author

    Paiagua, Sergio ; Pratas, Frederico ; Tomas, Pedro ; Roma, Nuno ; Chaves, Rafael

  • Author_Institution
    INESC-ID / IST, Tech. Univ. of Lisbon, Lisbon, Portugal
  • fYear
    2013
  • fDate
    23-26 Oct. 2013
  • Firstpage
    17
  • Lastpage
    24
  • Abstract
    Designing accelerating kernels is a comprehensive task that requires efficient coupling of hardware and software. In particular, the structures responsible for handling data transfers in multi-core accelerator-based systems play a crucial role in the resulting performance. This paper proposes a data streaming accelerator framework that provides efficient data management facilities that are easily tailored for any application and data pattern. This is achieved through an innovative and fully programmable data management structure, implemented with two granularity levels. The obtained results show that the proposed framework is capable of efficient address generation and data fetch for complex streaming data patterns, while significantly reducing the size occupied by the pattern description. A large matrices multiplication case-study, based on a streaming architecture with four sub-block multiplication cores, demonstrates that, by enabling data re-use, the proposed framework increases the available bandwidth by 4.2x, resulting in a performance speedup of 2.1x. Furthermore, it reduces the Host memory requirements and its intervention by more than 40x.
  • Keywords
    data handling; integrated circuit design; matrix multiplication; microprocessor chips; multiprocessing systems; operating system kernels; performance evaluation; HotStream; address generation; complex pattern data streaming; data fetch; data management facilities; data reuse; data streaming accelerator framework; data transfer handling; granularity levels; hardware coupling; matrix multiplication case-study; multicore accelerator-based systems; multiple accelerating kernels; programmable data management structure; software coupling; subblock multiplication cores; Automatic generation control; Backplanes; Engines; Hardware; Memory management; Streaming media; Many-Core Heterogeneous Architectures; Programmable Data (pre-)fetch Controller; Stream Computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture and High Performance Computing (SBAC-PAD), 2013 25th International Symposium on
  • Conference_Location
    Porto de Galinhas
  • Print_ISBN
    978-1-4799-2927-6
  • Type

    conf

  • DOI
    10.1109/SBAC-PAD.2013.17
  • Filename
    6702575