DocumentCode :
668077
Title :
Scalable Many-Field Packet Classification on Multi-core Processors
Author :
Qu, Yun R. ; Shijie Zhou ; Prasanna, Viktor K.
Author_Institution :
Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fYear :
2013
fDate :
23-26 Oct. 2013
Firstpage :
33
Lastpage :
40
Abstract :
Packet classification matches a packet header against the predefined rules in a rule set, it is a kernel function that has been studied for decades. A recent trend in packet classification is to match a large number of packet header fields. For example, the flow table lookup in Software Defined Networking (SDN) requires 15 fields of the packet header to be examined. Another trend in packet classification is to use software-based solutions employing multi-core general purpose processors and virtual machines. Although packet classification has been widely studied, most existing solutions on multi-core systems target the classic 5-field packet classification, their performance cannot be easily scaled up for a larger number of packet header fields. In this paper, we propose a decomposition-based packet classification approach, it supports large rule sets consisting of a large number of packet header fields. We first use range-tree and hashing to search each field of the input packet header individually in parallel. The partial results from all the fields are represented by bit vectors, they are merged in parallel to produce the final packet header match. We also balance the search and merge latencies, and employ software pipelining to further enhance the overall performance. We implement our approach on state-of-the-art multi-core processors, we evaluate its performance with respect to throughput and latency for rule set size ranging from 1K to 32K. Experimental results show that, for a 32K rule set, our algorithms can achieve an average processing latency of 2000 ns per packet and an overall throughput of 30 million packets per second on a state-of-the-art 16-core platform.
Keywords :
multiprocessing systems; pipeline processing; software performance evaluation; table lookup; trees (mathematics); virtual machines; 5-field packet classification; SDN; bit vectors; decomposition-based packet classification approach; flow table lookup; hashing; input packet header; kernel function; many-field packet classification; merge latency; multicore general purpose processors; multicore systems; overall performance; packet header fields; packet header match; performance evaluation; processing latency; range-tree; rule set; software defined networking; software pipelining; software-based solutions; state-of-the-art multicore processors; virtual machines; Field programmable gate arrays; Impedance matching; Multicore processing; Program processors; Throughput; Vectors; multi-core; packet classification; performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture and High Performance Computing (SBAC-PAD), 2013 25th International Symposium on
Conference_Location :
Porto de Galinhas
Print_ISBN :
978-1-4799-2927-6
Type :
conf
DOI :
10.1109/SBAC-PAD.2013.29
Filename :
6702577
Link To Document :
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