DocumentCode
668884
Title
Design and test of 2.5D and 3D stacked ICs
Author
Franzon, P.
fYear
2013
fDate
27-30 Oct. 2013
Abstract
Three dimensional chips stacked using Through Silicon Via (TSV) technology has been under consideration and the subject of intensive research for several years now. Soon the technologies will become available through standard fabs. Will the technology be an instant hit, a niche, or a flop? What is needed to ensure it reaches hit status? What are the basic manufacturing steps and flows? This tutorial will discuss these question mainly in the context of the opportunities and challenges that face the designer. What are the significant opportunities presented by 3DIC? What problems will the designer face that will need clever solutions? What are the potential solution paths?
Keywords
three-dimensional integrated circuits; 2.5D stacked IC; 3D stacked IC; 3DIC; TSV technology; three dimensional chips; through silicon via; Abstracts; Australia; Awards activities; Educational institutions; Face; Three-dimensional displays; Tutorials;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2013 IEEE 22nd Conference on
Conference_Location
San Jose, CA
Print_ISBN
978-1-4799-0705-2
Type
conf
DOI
10.1109/EPEPS.2013.6703444
Filename
6703444
Link To Document