SoC power integrity from early estimation to design signoff

Summary form only given. Power integrity has become a major integration challenge even for low power ARM-based SoC design. As performance requirements demand higher speed, more advanced process nodes reduce transistor level voltage margin, and low power consumption dictate aggressive power saving schemes such as more frequent power mode shifts and power gating, it´s challenging to satisfy the power integrity requirements. Following descriptions are some important aspects for SoC chip design.