Insertion loss characterization of tightly spaced interconnects with an embedded patterned layer

As smaller packaging footprints and faster data rates are pursued, signal integrity suffers as a result of interconnects routed in close proximity to one another. This paper focuses on two tightly spaced microstrips and highlights the use of an embedded patterned layer (EPL) of conductive elements to improve insertion loss and far end crosstalk. The frequency domain S-parameter performance is characterized with a commercial full wave solver and effective permittivity is extracted. The effect of relative permittivity on insertion loss is investigated. The largest improvement is seen for the permittivity of 10, with insertion loss improving from -6.3dB to -2.3dB at 67GHz. The same case shows a far end crosstalk improvement from -1.5dB to -4.8dB at 67GHz. However, a tradeoff with return loss and near end crosstalk is observed.