Title :
Power integrity analysis for core logic blocks
Author :
Dan Oh ; Razmadze, Alexander ; Chandrasekar, Karthik
Author_Institution :
Altera Corp., San Jose, CA, USA
Abstract :
In this paper, the new framework for power integrity analysis for core logic blocks is presented. Balancing on-chip timing budget becomes more challenging as both data and clock jitter increase due to large power noise. Conventional power integrity (PI) analysis focuses on reducing supply noise and does not provide timing jitter information. This paper proposes a general framework to model timing jitter due to supply noise. The proposed methodology can be used to define power distribution network (PDN) design requirements. This timing-based PDN design leads to significant reduction in the pessimism associated with either conventional target impedance concept, or static or dynamic power integrity analysis.
Keywords :
distribution networks; logic circuits; logic testing; power supply quality; timing circuits; timing jitter; PDN design requirements; clock jitter; core logic blocks; data jitter; dynamic power integrity analysis; on-chip timing budget; power distribution network design requirements; static power integrity analysis; supply noise; target impedance concept; timing-based PDN design; Clocks; Delays; Impedance; Jitter; Noise; Sensitivity; clock uncerntainty; core jitter; core timing; digital timing; power integrity; target impedance;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2013 IEEE 22nd Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4799-0705-2
DOI :
10.1109/EPEPS.2013.6703471
