Differential Through-Silicon-Vias modeling and design optimization to benefit 3D IC performance

Through Silicon Vias (TSVs) constitute key components interconnecting adjacent dies vertically to form three dimensional integrated circuit (3D IC). In this paper, we present an accurate electrical circuit model for differential through silicon vias (TSVs) considering the metal oxide semiconductor capacitance effects and study the effect of differential TSVs on the signal integrity with high data rate signals (up to 25Gbps) using eye diagram approach. Furthermore, we find the nonlinear TSV capacitance has the most predominant impact for the 3D IC performance, and thus, its negative effect to the system performance should be minimized. We optimize the parameters of TSVs architecture and manufacturing process to obtain the minimum depletion capacitance in the desired operating voltage region based on the nature of the TSVs C-V characteristics. Our study shows minimizing the TSVs capacitance could significantly improve the 3D IC performance, which help in developing effective design guidelines for TSVs in 3D IC.