Title :
Taylor-Kuznetsov fault-tolerant memories: A survey and results under correlated gate failures
Author :
Brkic, Srdan ; Ivanis, Predrag ; Djordjevic, Goran ; Vasic, Bane
Author_Institution :
Innovation Centre, Univ. of Belgrade, Belgrade, Serbia
Abstract :
This paper gives a brief survey of information theoretic results on fault-tolerant memory systems. The main focus is on Taylor-Kuznetsov memory architecture which has been shown to achieve nonzero computational capacity. A new approach for analyzing fault-tolerant memories that takes into account gate failure correlation is also presented. The analysis was done by modelling gate failures by Markov chain.
Keywords :
Markov processes; error correction codes; failure analysis; fault tolerance; integrated circuit reliability; parity check codes; storage management chips; LDPC codes; Markov chain; Taylor-Kuznetsov fault-tolerant memory system; Taylor-Kuznetsov memory architecture; error correcting codes; gate failure correlation; information theory; memory circuits; nonzero computational capacity; Circuit faults; Decoding; Fault tolerance; Fault tolerant systems; Logic gates; Parity check codes; Fault-tolerance; Fault-tolerant memory; Low-density parity-check codes; Taylor-Kuznetsov memory;
Conference_Titel :
Telecommunication in Modern Satellite, Cable and Broadcasting Services (TELSIKS), 2013 11th International Conference on
Conference_Location :
Nis
Print_ISBN :
978-1-4799-0899-8
DOI :
10.1109/TELSKS.2013.6704419