Concurrent generation of pseudo random numbers with LFSR of Galois type

Author

Milovanovic, Emina I. ; Milovanovic, Igor Z. ; Stojcev, Mile K.

Author_Institution

Fac. of Electron. Eng., Univ. of Nis, Nis, Serbia

Volume

01

fYear

2013

fDate

16-19 Oct. 2013

Firstpage

61

Lastpage

64

Abstract

In this paper we consider the implementation of parallel test patterns generation which is used as a basic building block in built-in-self test (BIST) design. The proposed design can drive several circuits under test (CUT) within a complex VLSI IC. For parallel test pattern generation a LFSR of Galois type is used. Mathematical procedure for concurrent pseudo random number (PRN) generation is described. We have implemented a LFSR that generates two PRNs in parallel. The achieved speed up is between 1.33 and 2, and depends on the characteristics of used primitive polynomial.

Keywords

VLSI; built-in self test; random number generation; shift registers; Galois type LFSR; built-in-self test design; circuits under test; complex VLSI IC; concurrent pseudo random number generation; linear feedback shift register; parallel test patterns generation; primitive polynomial; Built-in self-test; Clocks; Generators; Polynomials; Registers; Vectors; Very large scale integration; Built-In Self-Test; Linear Feedback Shift Register; Random Number Generator;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunication in Modern Satellite, Cable and Broadcasting Services (TELSIKS), 2013 11th International Conference on

Conference_Location

Nis

Print_ISBN

978-1-4799-0899-8

Type

conf

DOI

10.1109/TELSKS.2013.6704893

Filename

6704893