Standard definition ANPR system on FPGA and an approach to extend it to HD

Automatic Number Plate Recognition (ANPR) system becomes an important research topic in Intelligent Transportation systems (ITS). More recently, high-definition (HD) cameras are used for providing better performance in ANPR system. However, most known approaches for standard definition (SD) number plate localisation (NPL) are not suitable for real-time HD image processing as the real-time requirement cannot be met due to the computationally intensive cost of localising the number plate. In this paper, a solution to link previously designed architectures for NPL, character segmentation and character recognition in a SD ANPR system is first described. The system is to be implemented on a single stand-alone FPGA-based processing unit. An approach to extend the SD ANPR system to HD ANPR system without significantly increasing the computational cost is then introduced.