Prospects for high-aspect-ratio FinFETs in low-power logic

As we reduce transistor capacitances, node capacitances are limited by wiring, setting a minimum power dissipation determined by the number of gates, the mean wire length, the mean switching rate, and the supply voltage V_DD. With thermally-activated, FETs, the off-state leakage I_off and target on-current I_on then determine the minimum feasible V_DD, and the IC clock frequency can then be increased only at the expense of increased power consumption. Tunnel transistors [1] offer subthreshold characteristics steeper than 60mV/decade, but achieving high I_on at low I_off and low V_DD is challenging. Subthreshold logic [2] operates at lowV_DD, but is slow because of low I_on. Here we propose low-power logic using high-aspect-ratio finFETs, devices we have fabricated with few-nm body thicknesses and 180nm height [3]. If these can fabricated at ~20nm pitch, then the fin surface area can exceed its footprint area - i.e. the area the transistor occupies on the IC - by ~10:1. IC performance can be then improved by maintaining fixed V_DD, but with reduced FET footprint area hence reduced die size and therefore reduced wiring capacitance, or can be improved by reducing V_DD to ~300mV while maintaining large I_on per unit IC die area.