An efficient evaluation method for packaging interconnection

In general, power MOSFET die must be connected to the external circuit using a certain packaging method. Different packaging methods use different ways to connect the MOSFET die to pins or pads; for example, wire bonding, solid copper strap and so on. These packaging methods will introduce the packaging parasitic inductors (L), capacitors (C) and resistor (R) which has detrimental impacts on MOSFET switching characteristics, causing signal overshoot, EMI noise and switching energy loss. With the switching frequency of power circuits continually increasing, the system performance is increasingly affected by interconnection parasitic inductance. Operating power MOSFET devices at frequencies over 1MHz will pose significant challenges to established power electronic packages such as the D2-Pak and wire bonded SO-8 devices. In this paper an efficient evaluation method for packaging interconnection are presented. By using power loss analysis of different packaging interconnection for various design factors such as parasitic position, parasitic resistor, parasitic capacitor and parasitic inductor can generate an empirical correlation. This correlation is using statistical method to take account of all packaging interconnection parasitics (RLC) and representing a new “Interconnection Figure of Merit” (IFOM). The IFOM provides a basis for easily assessing and comparing the various packaging interconnection method. In essence the IFOM describes the cost and performance of packaging interconnection.