The 3-D parallel processor applied to matrix inversion

Matrix computation such as matrix addition, subtraction, multiplication and inversion are frequently used in various fields for research and engineering application. It is a very important tool for image processing, speech recognition and signal processing for spectral analysis and beam forming... etc... As the area of computer application has broadened, the quantity of data to be operated has greatly increased. With a serial machine as we have now in the 2-D computer system it is becoming too much time consuming in matrix computation to meet the applications. The speed of data processing can be increased or improved by using the 3-D parallel processor, a 3-D IC hardware machine. With the advancement of the TSV (Through Silicon Via), wafer to wafer interconnection and stacking technologies in 3-D IC manufacturing, it has become relatively easy and low cost to produce a 3-D parallel processor to meet the requirement for advance research and engineering. What will be the different between the 2-D and 3-D processor is that the processing algorithm and the circuit design architecture. A 3-D processor can be designed to execute the data signal paralleling while the conventional 2-D is sequentially. Therefore, the power of the 3-D data processing could be much greater than that of the 2-D version. This paper will describe how this 3-D IC design architecture for handling great number of data processing for matrix inversion as an example in comparing with the current 2D machine in processing power and execution time.