Design optimization for wafer level package reliability by using artificial neural network

An artificial neural network (ANN) based multi-objective design optimization for a wafer level package (WLP) is presented. Design factors including bump pad configuration, solder alloy composition, bump pad opening diameter, pad overhang (Cu pad radius minus pad opening radius), redistribution layer (RDL) polymer dielectric thickness and under-bump Cu thickness are grouped and considered by using a 3-level full factorial design of simulations (DoS) procedure. Key failure indices corresponding to solder joint fatigue fracture, RDL trace fatigue fracture and polymer dielectric cracking are selected as the objective functions for the design optimization. The Pareto optimal solutions are determined by using a genetic algorithm, and the compromise programming method is applied to determine the most reliable design.