Temperature rise minimization through simultaneous layer assignment and thermal through-silicon-via planning

Because of the reduction of wire length, three-dimensional integrated circuit (3D IC) technology can improve the circuit speed and reduce the power dissipation. However, the heat generated by the stacked layers may result in a very large amount of temperature rise. Therefore, in the design of three-dimensional integrated circuit, it is very important to reduce the temperature rise. Although previous works have addressed the relation between layer assignment and temperature rise, they do not consider the utilization of thermal through-silicon-vias (TSVs). Based on that observation, in this paper, we are motivated to perform simultaneous layer assignment and thermal TSV planning for further temperature rise reduction. We propose an integer linear programming approach to solve this problem optimally. Compared with previous works, experimental results show that our ILP approach can achieve a large amount of temperature rise reduction.