TSV-less BSI-CIS wafer-level package and stacked CIS module

In this study, a back-side illuminated CMOS image sensor (BSI-CIS) without through-silicon via (TSV) is developed with thin wafer handling combination with ultra-wafer thinning technologies. The CIS wafer is implemented front-side processes then temporarily bonded on a Si carrier by Brewer Science adhesive with ZoneBOND™ technology applied. The ZoneBOND™ technology provides a promising solution for thin wafer handling with temporary bonding, wafer thinning, thin wafer processes, and de-bonding. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent dipping for de-bonding. The thickness of BSI-CIS without TSV is less than 5μm, which is visible light transparent to meet the back-side illumination requirement. Cu/Sn bumps with 50μm size are formed with the bump height uniformity less than 5% in wafer level. The completed BSI-CIS is then assembled on Si substrate. There are totally 400 bumps in this test vehicle design. The Cu/Ni/Au UBMs on Si substrate bonded with Cu/Sn bumps on CIS is conducted by thermal compression bonding. The wafer-level package of TSV-less BSI-CIS has been successfully developed and demonstrated, stacked module is accomplished and passed 1000 cycles of -55°C~125°C TCT in the paper.