In Situ Characterization of Bias Instability in Bare SOI Wafers by Pseudo-MOSFET Technique

Bias instability is a reliability issue affecting the electrical characteristics of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability of bare SOI wafers using the pseudo-MOSFET technique. The effect of positive and negative stress pulses on the properties of both hole and electron channels is systematically investigated using measure-stress-measure and on-the-fly methods. The origin of the instability, the dependence of the degradation with time, and the recovery after the stress are discussed.