Title :
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD process technology
Author :
Kumar, Ajit ; Hapsari, Emita Yulia ; Kumar, Vipin ; Mrinal, Aryadeep ; Sheu, G. ; Shao-Ming Yang ; Ningaraju, Vivek
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, Taiwan
Abstract :
In this work, a single RESURF P-top layer with STI-sided N-LDMOS device is developed to realize a breakdown voltage of 20V-60V with lowest on-resistance and good charge balance which is demonstrated by using three-dimensional Sentaurus process and device simulators. By tuning not only the doping concentration in substrate, N-drift and P-top layer regions, but also the width ratio of N-drift region divided by STI one (WN-drift/WSTI), a low specific on-resistance while maintaining a high breakdown voltage can be achieved successfully in this work.
Keywords :
BiCMOS integrated circuits; doping profiles; power MOSFET; semiconductor device breakdown; semiconductor device models; BCD process technology; N-drift region; STl-sided N-LDMOS device; breakdown voltage; device simulators; doping concentration; laterally diffused MOSFET; on-resistance high voltage 3D NLDMOS; single RESURF P-top layer; size 0.18 mum; three-dimensional Sentaurus process; voltage 20 V to 60 V; Doping; Resistance; Silicon;
Conference_Titel :
Nanotechnology Materials and Devices Conference (NMDC), 2013 IEEE 8th
Conference_Location :
Tainan
Print_ISBN :
978-1-4799-3386-0
DOI :
10.1109/NMDC.2013.6707459
