Comparative study of process variations in junctionless and conventional double-gate MOSFETs

This work presents an in-detail investigation of process variations in symmetrical junctionless double-gate CMOS using 2D numerical simulation. General variability issues including oxide thickness, gate work function, and channel thickness are discussed. Uniform probability density function was assumed for the dopant atom location in the junctionless channel. Based on the statistical doping profiles, device simulation was performed by solving 2D drift-diffusion equations with modified local density approximation as used mostly in bulks device for quantum confinement. This paper is organized as follows. Section II introduces the simulation technique for device structure. Section III presents a comprehensive analysis for impact of process fluctuations on threshold voltage. Finally, conclusions are drawn.