Tin (Sn) for enhancing performance in silicon CMOS

Author

Hussain, Aftab M. ; Fahad, Hossain M. ; Singh, Navab ; Torres Sevilla, Galo A. ; Schwingenschlogl, U. ; Hussain, M.M.

Author_Institution

Integrated Nanotechnol. Lab., King Abdullah Univ. of Sci. & Technol., Thuwal, Saudi Arabia

fYear

2013

fDate

6-9 Oct. 2013

Firstpage

13

Lastpage

15

Abstract

We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon.

Keywords

CMOS integrated circuits; MOS capacitors; ab initio calculations; elemental semiconductors; high-k dielectric thin films; silicon; tin; MOSCAP; Si-Sn; channel material; electrical properties; first-principle study; group IV element; high-K-metal gate based metal-oxide-semiconductor capacitors; silicon CMOS; Gold; Large scale integration; Logic gates; Performance evaluation; Silicon; Switches; Three-dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology Materials and Devices Conference (NMDC), 2013 IEEE 8th

Conference_Location

Tainan

Print_ISBN

978-1-4799-3386-0

Type

conf

DOI

10.1109/NMDC.2013.6707470

Filename

6707470