Title :
Process integration of best in class specific-on resistance of 20V to 60V 0.18µm bipolar CMOS DMOS technology
Author :
Hapsari, Emita Yulia ; Kumar, Ravindra ; Sheu, G. ; Shao-Ming Yang ; Anil, T.V.
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, Taiwan
Abstract :
The evolution of Bipolar CMOS DMOS (BCD) technology leads in the improvement of design technology to produce better device performance with fabrication cost effectiveness as concerned. In this paper, 0.18μm BCD technology with linear p-top layer N-channel LDMOS structure from 20V to 60V is presented with best in class Ron for both N-channel and P-channel LDMOS compared to recent BCD technology works. The optimization of current gain of 20V BJT has been done by adjustment of emitter width and boron doping concentration of base with increasing of current gain up to ten times higher without significantly change the breakdown voltage.
Keywords :
BiCMOS integrated circuits; CMOS integrated circuits; boron; circuit optimisation; doping profiles; electric breakdown; electric resistance; integrated circuit design; P-channel LDMOS; bipolar CMOS DMOS technology; boron doping concentration; breakdown voltage; class specific-on resistance; current gain optimization; design technology; emitter width adjustment; fabrication cost effectiveness; linear p-top layer N-channel LDMOS structure; process integration; size 0.18 mum; voltage 20 V to 60 V; CMOS integrated circuits; CMOS technology; Current density; Electric breakdown; Fabrication; MOS devices;
Conference_Titel :
Nanotechnology Materials and Devices Conference (NMDC), 2013 IEEE 8th
Conference_Location :
Tainan
Print_ISBN :
978-1-4799-3386-0
DOI :
10.1109/NMDC.2013.6707471
