An FPGA-based fixed-point architecture for binary logarithmic computation

Real-time numerically intensive image processing applications demand dedicated hardware for various complex arithmetic functions. These arithmetic functions can be efficiently implemented by employing a binary logarithmic circuit. In this paper a field-programmable gate array (FPGA) based architecture for the binary logarithm approximation unit is proposed. The proposed architecture utilizes combinational logic circuit elements and fixed-point datapath. The implemented architecture is capable of finding approximated logarithm of an integer number, integer with fractional number and only fractional number. The architecture uses the same set of circuit elements for all computations. In the implemented architecture eight-region approximations is used. The proposed architecture is implemented in a Xilinx Virtex-5 xc5vfx70t FPGA device. The available FPGA macros are utilized for the elementary circuit elements. The device utilization summery shows that the proposed architecture consumes minimal FPGA resources. The error analysis, performed with multiple sets of random numbers, illustrates that the proposed architecture has very nominal error associated with both the fractional as well as fixed-point numbers.