Data — Clock setup and hold times margins correction method in high speed serial links

A method of serial links output data and clock signals setup and hold times correction presented in this paper. The proposed architecture produces corrected clock which have enough setup/hold time margins respect data signal over PVT, which is needed to avoid data errors and setup/hold violations during further operation with data. The presented correction mechanism can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.