Power optimization of single precision floating point FFT design using fully combinational circuits

This paper focused on the design of 32 bit IEEE 754 single precision floating point architecture for 8 point FFT. The total design is in combinational form. The FFT design is simulated in Active HDL. Results are verified with MATLAB simulation. Correctness is obtained up to twenty two bit. The design is tested for complex input data (separately for real and imaginary data). For low power design pipelining is used i.e. forward path cutset to FFT stages. Using two stages pipelining, the power of architecture is calculated in Design Vision tool of Synopsys by 45nm technology file. By this scheme, the total power required is reduce up to 35%.