DocumentCode
674864
Title
Viterbi Decoders Generation for FPGA Platforms
Author
Espinosa, Luis Alberto Luna ; De Dios Lopez Sanchez, Juan ; Hipolito, Juan Ivan Nieto ; Vazquez Briseno, Mabel ; Ramos, Aldo E. Perez ; Reyes, Salvador Villareal
Author_Institution
Univ. Autonoma de Baja California, Baja, CA, USA
fYear
2013
fDate
19-22 Nov. 2013
Firstpage
211
Lastpage
215
Abstract
In this paper, we describe a relation that allows to generate Viterbi decoders for FPGA platforms. These decoders are created from the vectors that describe the adders of a convolutional encoder with code rate 1/2. This relation has been used to implement a script in Mat lab, which generates decoders in VHDL language for an FPGA platform from a basic set of entities used to create ACS cells.
Keywords
Viterbi decoding; channel coding; convolutional codes; field programmable gate arrays; hardware description languages; ACS cells; FPGA platforms; Matlab; VHDL language; Viterbi decoders generation; add-compare-select cells; channel codings; convolutional encoder; Communication systems; Convolutional codes; Decoding; Field programmable gate arrays; Measurement; Registers; Viterbi algorithm; FPGA; Viterbi decoder;
fLanguage
English
Publisher
ieee
Conference_Titel
Mechatronics, Electronics and Automotive Engineering (ICMEAE), 2013 International Conference on
Conference_Location
Morelos
Print_ISBN
978-1-4799-2252-9
Type
conf
DOI
10.1109/ICMEAE.2013.32
Filename
6713980
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