A hierarchical layout generation method for quantum circuits

Quantum circuit design flow consists of two main tasks: synthesis and physical design. Synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. Quantum physical design problem is intractable. This process can be divided into two main processes: scheduling and layout generation. Some heuristic techniques have been proposed for the layout generation. These techniques do not produce good layouts for large netlists in terms of latency. Focusing on this issue, in this paper, a hierarchical layout generation algorithm is proposed that generates better layouts in terms of latency. Ion trap is used as the underlying technology in this paper. Experimental results show that the proposed algorithm decreases the average latency of quantum circuits by about 22% for the attempted benchmarks.