An ultra wideband, 6–9 GHz, 130 nm CMOS low noise amplifier

In this paper we present a low noise amplifier designed to operate in the ultra wideband upper band (6-9 GHz) using the 130 nm CMOS technology process. The main goals are high linearity, low variance of the gain over the operating range, low consumption and robustness to process variations. A two stage (common gate, common source) topology yields IIP3 of up to 0.73 dBm and S₂₁ of 14.20 dB with the variation of ±0.80 dB over the range in question. Maximum noise factor value is 5.10 dB, and both input and output return loss are less than -10 dB. The power dissipation is 18.41 mW from the supply voltage V_DD=1.20 V. Corner analysis shows that the circuit retains its properties even in the worst case scenarios. The results given are obtained through the schematic level simulations using Spectre Simulator from Cadence Design System.