3D hetero-integration technology with backside TSV and reliability challenges

Recently, hetero-integrated system (3-D super chip) involving memory, processor, power ICs, sensor, and photonic circuits has attracted attention owing to its high performance, highspeed communication, multi-functionality, and low power consumption . However, heterointegration of devices with different functions has many technical challenges owing to various types of size, thickness, and substrate because they were fabricated by different technologies. In addition, current 3-D integration technologies have another challenge such as high manufacturing cost and long prototyping time to achieve 3-D super chip. To realize 3-D super-chip with low-cost, high flexibility, and rapid prototyping time, we proposed die-level 3-D hetero-integration technology with fine-size backside TSV. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die-level. To fabricate 3-D super chip, each functional chip should be thinned to 10-50μm thickness. However, the ultra-thin nature of Si substrate leads to several problems such as weak mechanical strength, warping, local deformation, and residual stress in the stacked die. In addition, the large CTE difference between Si substrate and Cu TSV and μ-bump is posing risks of undesired thermo-mechanical stress generation and Cu contamination. In this paper, we describe new 3-D heterointegration technology with backside TSV for realizing 3-D super chip with low-cost, high flexibility, and rapid prototyping time and address our attention on some of the most potent reliability issues such as thermo-mechanical stress, crystal defects, and Cu contamination introduced in 3-D integration processes.