A 44μW/10MHz minimum power operation of 50K logic gate using 65nm SOTB devices with back gate control

Author

Morohashi, Shotaro ; Sugii, Nobuyuki ; Iwamatsu, Takanori ; Kamohara, Shiro ; Kato, Yu ; Cong-Kha Pham ; Ishibashi, Koji

fYear

2013

fDate

7-10 Oct. 2013

Firstpage

1

Lastpage

2

Abstract

Performance, leakage and Emin on 65-nm SOTB and bulk were compared. We evaluated ring oscillators for SOTB and bulk with the same layout pattern. It is shown that operation frequency can be controlled from 6MHz to 40MHz, leakage of sleep mode can be decreased by 3 orders of magnitude on SOTB. By applying adjustable body bias and supply voltage depending on frequency, energy of 50k gates CMOS logic circuit can be minimized to be 4.4pJ/Hz, which corresponds to 44μW at 10MHz. Leakage of the logic gates can be reduced at 4.2nA at sleep mode.

Keywords

CMOS logic circuits; integrated circuit layout; logic gates; low-power electronics; silicon-on-insulator; CMOS logic circuit; SOTB devices; back gate control; frequency 6 MHz to 40 MHz; layout pattern; logic gate; minimum power operation; operation frequency; power 44 muW; ring oscillators; size 65 nm; Frequency control; Inverters; Logic gates; Performance evaluation; Ring oscillators; Threshold voltage; Voltage measurement; Body Bias; Energy Reduction; SOTB;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/S3S.2013.6716586

Filename

6716586