Design of high-performance unified image scaler circuit for real-time object detection

This paper describes the design of high-performance unified image scaler circuit for real-time object detection. The proposed circuit generates nine scaled images at the same time for each VGA image. Each scaled image has a different level of resolution with the scaling factor of 0.8. In order to provide the real-time processing capability, original image data are stored in internal memories and reused to generate nine resized images. In addition, the operation of bilinear interpolation is shared in order to reduce the circuit size. We described the high-performance unified image scaler circuit using Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The synthesized circuit consists of 20,452 gates and its maximum operating frequency is 254MHz. Since the proposed circuit processes 24 640×480 image frames per second and generates nine resized images for each 640×480 image frame, it can be applied in many applications such as real-time object detection.