DocumentCode :
676382
Title :
FPGA Blokus Duo Solver using a massively parallel architecture
Author :
Yoza, Takashi ; Moriwaki, Retsu ; Torigai, Yuki ; Kamikubo, Yuki ; Kubota, Takahide ; Watanabe, Toshio ; Fujimori, Takumi ; Ito, H. ; Seo, Munkyo ; Akagi, Kouta ; Yamaji, Yuto ; Watanabe, Manabu
Author_Institution :
Electr. & Electron. Eng., Shizuoka Univ., Hamamatsu, Japan
fYear :
2013
fDate :
9-11 Dec. 2013
Firstpage :
494
Lastpage :
497
Abstract :
Recently, many game programs have been developed aggressively as hardware on field programmable gate arrays (FPGAs) because of the extremely large solution space of such games as the Connect6 game, Blokus Duo game, and others so that the computational capabilities of computers are currently insufficient to search all possible solutions. This report describes an FPGA acceleration experiment for the Blokus Duo game. The FPGA Blokus Duo Solver was implemented on an Arria II GX FPGA (Altera Corp.). Its operation speed is 25 times faster than C++ based software operation of the same algorithm on a Core i7 processor.
Keywords :
computer games; field programmable gate arrays; parallel architectures; Arria II GX FPGA; Blokus Duo game; C++ based software operation; Connecta game; Core i7 processor; FPGA Blokus Duo Solver; FPGA acceleration experiment; computational capability; field programmable gate array; game program; massively parallel architecture; operation speed; Algorithm design and analysis; Computers; Conferences; Field programmable gate arrays; Games; Hardware; Software;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology (FPT), 2013 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4799-2199-7
Type :
conf
DOI :
10.1109/FPT.2013.6718426
Filename :
6718426
Link To Document :
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