Title :
Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench
Author :
Sugimoto, Naozo ; Miyajima, Teruyuki ; Kuhara, Takuya ; Katuta, Yuki ; Mitsuichi, Takushi ; Amano, Hideharu
Author_Institution :
Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan
Abstract :
This paper presents a design of an FPGA-based Blokus Duo solver. It searches a game tree by using the miniMax algorithm with alpha-beta pruning and move ordering. In addition, HLS tool called CyberWorkBench (CWB) is used to implement hardware. By making the use of functions in CWB, parallel fully pipelined design is generated. The implemented solver works at 100MHz with Xilinx Spartan-6 XC6SLX45 FPGA on the Digilent Atlys board. It can search states after three moves in most cases.
Keywords :
artificial intelligence; field programmable gate arrays; game theory; logic design; minimax techniques; trees (mathematics); CWB; CyberWorkBench; Digilent Atlys board; FPGA-based Blokus Duo solver; HLS tool; Xilinx Spartan-6 XC6SLX45 FPGA; alpha-beta pruning; artificial intelligence; frequency 100 MHz; game tree; minimax algorithm; move ordering; parallel fully pipelined design; Algorithm design and analysis; Clocks; Field programmable gate arrays; Games; Hardware; Registers; Tiles;
Conference_Titel :
Field-Programmable Technology (FPT), 2013 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4799-2199-7
DOI :
10.1109/FPT.2013.6718427
