Efficient intra prediction VLSI architecture for HEVC standard

Intra prediction with fine directions is a critical feature in the new High Efficiency Video Coding (HEVC) standard because it provides significant performance gain. Different from the intra prediction in the H.264/AVC, this approach is more complicated in terms of computation and memory access, which makes the VLSI design very difficult. In this paper, with the analysis of the algorithm of the DC prediction mode and the planar prediction mode in HM, a reused adder VLSI architecture for DC mode and a high efficient VLSI architecture for planar mode are proposed for intra prediction. Implementation with TSMC 90 nm CMOS technology indicates that the proposed architecture can work at 357MHz operation frequency and 12970 logic gates acquired for DC prediction and can work at 308 MHz operation frequency and 57500 logic gates acquired for planar prediction. The processing latency of the proposed VLSI architecture can support the real-time processing of 4:2:0 format 4096×2048@30fps video sequences.