Low power and area optimized Truncated Multiplier architecture

This paper proposes a low error and power optimized architecture for the multiplier based on multiplexers that aims for an optimized truncated product and power. The design of efficient truncation scheme with minimum truncation error and low power multiplier is essential for VLSI implementation of Signal Processing Devices. Various conventional array and parallel multipliers have been used and many of them boost the speed of the device at the cost of large VLSI area and high power dissipation. A novel design for multiplier based on multiplexer has been proposed in this paper considering the existing multiplexer based architecture. The proposed low error and power optimized multiplexer based truncated Multiplier was implemented in HSPICE environment in TSMC 180 nm library technology files. The results obtained are tabulated in the simulation result section, and it is observed that the proposed truncated multiplier architecture consumes approximately 35% reduction in dynamic power with minimum error. It also reduces the number of transistors by 37% when compared to the existing multiplexer based multiplier the conventional multiplexer based multiplier for 8 × 8 bit multiplication operation.