DocumentCode
676931
Title
FPGA implemented reduced Ethernet MAC
Author
Suto, Jozsef ; Oniga, Stefan
Author_Institution
Fac. of Inf., Univ. of Debrecen, Debrecen, Hungary
fYear
2013
fDate
2-5 Dec. 2013
Firstpage
29
Lastpage
32
Abstract
This paper presents an implementation of a reduced Ethernet MAC. The reduced MAC is simple and not resource wasteful. Therefore it is suitable to every project which includes network communication. It is especially useful to low performance FPGAs. In practice, the FPGA boards are well applicable to implement network protocols because the implemented protocols will work in parallel. The main topics of the article cover the base concept of the reduced MAC, the implemented network protocols and the characteristics.
Keywords
access protocols; field programmable gate arrays; local area networks; Ethernet MAC; FPGA; network communication; network protocols; Clocks; Field programmable gate arrays; Hardware design languages; IP networks; Protocols; Servers; Wires; Ethernet; FPGA; MAC; MII; PHY;
fLanguage
English
Publisher
ieee
Conference_Titel
Cognitive Infocommunications (CogInfoCom), 2013 IEEE 4th International Conference on
Conference_Location
Budapest
Print_ISBN
978-1-4799-1543-9
Type
conf
DOI
10.1109/CogInfoCom.2013.6719258
Filename
6719258
Link To Document