Low power and area efficient implementation of BCD adder on FPGA

Decimal adders and multipliers are the basic building block for arithmetic and logical unit and barrel shifters in today´s high end processors and controllers. In this paper, an efficient BCD adder is designed based on low power synthesis technique at the architectural level. There are different levels of abstraction at which the power can be minimized but the low power technique at the architectural level has more impact than that of circuit level approaches. Two different approaches have been discussed i.e. pipelining and parallelism, so as to minimize the power consumption at architectural level. The proposed designs are tested and implemented using VHDL and the Xilinx ISE 10.1 targeting Xilinx XC5VLX30-3 FPGA. The result shows the optimization of power, delays and the area for different designs and a comparison analysis is provided based on the existing designs in the literature.